1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device formed by a process including a photolithography step of forming a resist pattern on a substrate having a step.
2. Description of Related Art
Conventionally, in order to form a desired resist pattern on a semiconductor substrate (wafer), a photoresist is deposited on a principal surface of the semiconductor substrate, and an exposure mask is positioned and aligned with the principal surface of the semiconductor substrate, and then, an energy ray such as light or an X-ray is irradiated through the exposure mask to the photoresist film deposited on the principal surface of the semiconductor, for exposure of the photoresist film, and thereafter, the exposed photoresist film is developed. Thus, the desired resist pattern is obtained on the semiconductor substrate
Referring to FIG. 1A, there is shown a diagrammatic plan view of two different level wiring conductors in a semiconductor device manufactured in accordance with one prior art process. FIGS. 1B, 1C and 1D are diagrammatic sectional views, taken along the line I--I in FIG. 1A, of a semiconductor device manufactured in accordance with the first prior art process and an exposure mask used in the first prior art process, for illustrating various recesses formed in the resist pattern because of halation which will be described later.
As shown in FIGS. 1A, 1B, 1C and 1D, a lower level wiring conductor pattern 12 is formed through an insulator film on a principal surface of a semiconductor substrate 11, and an interlayer insulator film 13 and an upper level wiring conductor film 14 are formed in the named order on the lower level wiring conductor pattern 12 and the semiconductor substrate 11. A positive photoresist film 15 is deposited on the upper level wiring conductor film 14, and is exposed by utilizing an exposure mask 16 having a light blocking pattern 17. Thereafter, the photoresist film 15 is developed to obtain a resist pattern 15A.
However, the prior art process has such a disadvantage that, if on the substrate 11 there exists a step "S" attributable to the lower level wiring conductor pattern 12, the resist pattern 15A precisely corresponding to the light blocking pattern 17 of the exposure mask 16 cannot be obtained. The reason for this disadvantage is considered that, irradiation light 18 is reflected by the surface of the upper level wiring conductor film 14 in the step "S" into an oblique direction (halation), so that a portion of the photoresist film 15 to be shielded by the light blocking pattern 17 is exposed to an undesired reflection light causing the halation.
In particular, as shown in FIGS. 1A, 1B, 1C and 1D, in a bent or angled portion 12A of the lower level wiring conductor pattern 12, the step forms a three-dimensionally curved concave surface, so that by action of a concave mirror effect, a light 10 reflected by the step in the angled portion 12A is collected to one point or small area 19 of the photoresist which should be shielded from the exposure light, with the result that the photoresist of the point or small area 19 is intensely exposed. Thus, in some cases, a recess 19B as shown in FIG. 1B is formed at a middle portion in a height of the resist pattern 15A, and in other cases, a notch or groove 19C as shown in FIG. 1C is formed which extends from a middle portion in a height of the resist pattern 15A to a top of the resist pattern 15A. In extreme cases, a hole 19D as shown in FIG. 1D is formed which penetrates through a middle portion of the resist pattern 15A.
When the upper level wiring conductor film 14 is etched and patterned by using the resist pattern thus formed, to form an upper level wiring conductor pattern 14A, a narrow portion 19A is formed in the upper level wiring conductor pattern 14A, as shown in FIG. 1A. The upper level wiring conductor pattern 14A is easily destroyed or disconnected at the narrow portion 19A, and therefore, the semiconductor device having a satisfactory reliability cannot be obtained.
In order to eliminate the above mentioned disadvantage caused by the halation, Japanese Patent Application Pre-examination Publication No. JP-A-05-074701, (an English abstract of which is available from the Japanese Patent Office, and the content of the English abstract of JP-A-05-074701 is incorporated by reference in its entirety into this application) proposes to use an exposure mask 16A having a dummy mask pattern 17A at a position corresponding to the step "S" on the surface of the substrate 11, in addition to the light block pattern 17 required inherently, as shown in FIG. 2. The provision of the dummy mask pattern 17A prevents the step "S" from being irradiated with the exposure light 18, so that the halation is prevented, and therefore, a highly precise resist pattern can be obtained.
In this second prior art process, however, not only the resist pattern 15A corresponding to the inherent light blocking pattern 17 but also the resist pattern 15B corresponding to the dummy mask pattern 17A are formed from the photoresist 15. Therefore, when the upper level wiring conductor film 14 is etched by using the resist patterns thus patterned, there is formed an isolated or floating pattern of the upper level wiring conductor film 14 which does not contribute a circuit operation. Rather, this isolated or floating pattern of the upper level wiring conductor film 14 generates a parasite capacitance to adjacent wiring layers, with the result that a signal transmission speed drops. On the other hand, if the floating pattern of the upper level wiring conductor film 14 is fine or small, the floating pattern is collapsed or peeled off, so that the collapsed or peeled-off floating pattern remains as a foreign matter on the substrate, which causes a short-circuiting between wiring conductors, and therefore, which lowers reliability of the semiconductor device.
Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-62-135837, (an English abstract of which is available from the Japanese Patent Office, and the content of the English abstract of JP-A-62-135837 is incorporated by reference in its entirety into this application) proposes to use an exposure mask 16D having a dummy pattern 17B having a size smaller than a limit of resolution above the step "S" on the surface of the substrate 11, as shown in FIG. 3. This dummy pattern 17B prevents the step "S" from being directly irradiated with the exposure light 18, and also, presents formation of the above mentioned floating pattern because a diffraction light generated by the dummy pattern 17B is irradiated onto the step "S" and therefore because a resist pattern is not formed on the step "S".
However, although the third prior art method as mentioned above can prevent the formation of the floating pattern, the diffraction light is irradiated onto the step "S". This diffraction light is weaker than the direct irradiation light, but the light reflected by the bent portion of the lower level wiring conductor pattern 12 is collected, with the result that influence of halation is still non-negligible, and it is still difficult to form a highly precise resist pattern. Furthermore, since the dummy pattern 17B is small in size, it is impossible to complete shield the step "S", and it is difficult to prevent the halation caused by the direct irradiation light.